Semi-conductor components, for instance corresponding integrated (analog and/or digital) computing circuitry, semi-conductor memory components such as for instance function storage components (PLAs, PALs, etc.) and table storage components (for instance ROMs or RAMs, in particular SRAMs and DRAMs), etc. are subjected to numerous tests during and after manufacture.
For instance components (semi-complete and still on the wafer) may be, at one or more stations and with the aid of one or more test apparatuses—even before the wafer has been subjected to all required process steps (i.e. even while the semi-conductor components are still in a semi-complete state)—subjected to appropriate test procedures (for instance so-called kerf measurements on the wafer scoring grid).
After completion (i.e. after all the wafer processing steps have been performed) the semi-conductor components can be subjected to further test procedures at one or more (further) test stations, for instance the components still present on the wafer and completed may be appropriately tested (“slice tests”) with the aid of corresponding (further) test equipment.
After the wafer has been sliced (and/or scored and snapped off) the—now individually available components, loaded into so-called carriers (packages)—can be subjected to further test procedures at one or more (further) test stations.
In similar fashion, one or more further tests can be performed (at corresponding further test stations and by using appropriate further test equipment) for instance after the semi-conductor components have been installed in a corresponding semi-conductor component housing, and/or for instance after the semi-conductor component housings (with the semi-conductor components built into them in each case) have been installed in corresponding electronic modules (for so-called module tests), etc.
To ensure that semi-conductor components can function faultlessly within the total specified temperature range (for instance 0° C.–70° C.), the semi-conductor components may—before and/or during one or more of the above tests (for instance the above slice tests, carrier tests, module tests, etc.)—be appropriately heated or cooled in appropriate heating chambers.
The problem that occurs is that relatively strong non-homogeneous temperature distributions may occur in sections of the heating chamber.
This may for instance have the effect—for instance during a module test—that the most strongly heated semi-conductor component of an electronic module which has been introduced into the heating chamber may be heated relatively strongly, for instance 10° C. more than the least strongly heated semi-conductor component in one and the same module in the heating chamber.
This may lead thereto that one or more of the semi-conductor components in the heating chamber is heated too strongly (for instance above and/or far above the specified temperature in each case, or the target temperature), i.e. is “over-tested”.
Thereby the corresponding semi-conductor component may be irreparably damaged and/or destroyed.
In this way the targeted yield (i.e. the proportion of faultlessly operating semi-conductor components/modules) of all the semi-conductor components and/or modules being manufactured is reduced.
When an attempt is made to avoid the above “over-testing”—i.e. the excessive overheating—of those semi-conductor components which are arranged on each module and heated too strongly in the heating chamber due to the non-homogeneous temperature distribution occurring in the heating chambers, it may occur that the remaining semi-conductor components provided on the corresponding module in the heating chamber may not be heated strongly enough.
This may lead to a deterioration in the quality of the produced components and/or modules (because the danger increases that components and/or modules are produced that do not function faultlessly over the whole specified temperature range in each case).